AI4100 datasheet(10/18 Pages) A1PROS

10 / 18 page

Control

DOUT synchronizes to OUTCK

DOUT changes at OUTCK falling edge

ADCLK clock inversion

ADIN signal to PGA

ADIN signal to ADC

Reserved

ADC output high-Z, or logic of STBY

Black level reset, or logic of RESET

Power down, or logic of STBY

Fast clamp ±100μA

No clamp for ADIN

Clamp REFIN only

Clamp CCDIN only

Clamp off

S/H control polarity inversion

Enable control polarity inversion

Both of S/H and enable inversion

CDS signal to monitor

PGA output monitor

Output REFIN and CCDIN

CDS gain=6.02 dB

CDS gain=12.04 dB

CDS gain=-1.94 dB

Always high gain

Mode 1

Operations

DOUT synchronizes to ADCLK

DOUT changes at OUTCK rising edge

Normal operation as timing chart

ADIN function OFF

Reserved

Normal operation, ADC data output

Normal operation

Mode 2

Normal clamp ±50μA

Clamp operation active for ADIN

Normal mode, clamp both REFIN and CCDIN

Normal operation as timing chart

Monitor off

Mode 3

CDS gain=0 dB

Boost control on

Black loop gain

boost

CDS gain

control

Monitor

selection

S/H, enable

logic

Clamp target

ADIN clamp

Clamp current

Power down

Black level reset

ADC output

Reserved

ADIN

connection

ADCLK polarity

OUTCK polarity

DOUT timing

control

i4100

AI4100 bảng dữ liệu(PDF) 10 Page - A1 PROs co., Ltd.

AI4100 bảng dữ liệu(HTML) 10 Page - A1 PROs co., Ltd.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

bảng dữ liệu tải về

Link URL