CDK1306CSO28 datasheet(9/11 Pages) CADEKA

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Data Sheet

Figure 4. Ladder Force/Sense Circuit

Figure 5. Reference Ladder Circuit

Typically, the top side voltage drop for VRHF to VRHS will

equal:

VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical)

and the bottom side voltage drop for VRLS to VRLF will

equal:

VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical)

Figure 5 shows an example of expected voltage drops for

a specific case. VREF of 4.0V is applied to VRHF, and VRLF

is tied to AGND. A 90mV drop is seen at VRHS (= 3.91V),

and a 75mV increase is seen at VRLS (= 0.075V).

Analog Input

VIN is the analog input. The input voltage range is from

VRLS to VRHS (typically 4.0V) and will scale proportionally

with respect to the voltage reference. (See Voltage Refer-

ence section.)

The drive requirements for the analog inputs are very

minimal when compared to most other converters due to

the CDK1306 extremely low input capacitance of only 5pF

and very high input resistance of 50kΩ.

The analog input should be protected through a series

resistor and diode clamping circuit as shown in Figure 6.

Figure 6. Recommended Input Protection Circuit

Calibration

The CDK1306 uses an auto-calibration scheme to ensure

10-bit accuracy over time and temperature. Gain and

offset errors are continually adjusted to 10-bit accuracy

during device operation. This process is completely trans-

parent to the user.

Upon powerup, the CDK1306 begins its calibration

algorithm. In order to achieve the calibration accuracy

required, the offset and gain adjustment step size is a

fraction of a 10-bit LSB. Since the calibration algorithm

is an oversampling process, a minimum of 10,000 clock

cycles are required. This results in a minimum calibration

time upon powerup of 250μs (for a 40MHz clock). Once

calibrated, the CDK1306 remains calibrated over time and

temperature.

Since the calibration cycles are initiated on the rising edge

of the clock, the clock must be continuously applied for

the CDK1306 to remain in calibration.

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