SN54HC74, SN74HC74

DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCLS094D – DECEMBER 1982 – REVISED JULY 2003

4

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC74

SN74HC74

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

4.2

5

fclock

Clock frequency

4.5 V

31

21

25

MHz

6 V

0

36

0

25

0

29

2 V

100

150

125

PRE or CLR low

4.5 V

20

30

25

t

Pulse duration

6 V

17

25

21

ns

tw

Pulse duration

2 V

80

120

100

ns

CLK high or low

4.5 V

16

24

20

6 V

14

20

17

↑

2 V

100

150

125

↑

Data

4.5 V

20

30

25

t

Setup time before CLK

↑

6 V

17

25

21

ns

tsu

Setup time before CLK

↑

2 V

25

40

30

ns

PRE or CLR inactive

4.5 V

5

8

6

6 V

4

7

5

↑

2 V

0

0

0

th

Hold time, data after CLK

↑

4.5 V

0

0

0

ns

6 V

0

0

0

(unless otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC

TA = 25°C

SN54HC74

SN74HC74

UNIT

PARAMETER

(INPUT)

(OUTPUT)

VCC

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

6

10

4.2

5

fmax

4.5 V

31

50

21

25

MHz

6 V

36

60

25

29

2 V

70

230

345

290

PRE or CLR

Q or Q

4.5 V

20

46

69

58

t d

6 V

15

39

59

49

ns

tpd

2 V

70

175

250

220

ns

CLK

Q or Q

4.5 V

20

35

50

44

6 V

15

30

42

37

2 V

28

75

110

95

tt

Q or Q

4.5 V

8

15

22

19

ns

6 V

6

13

19

16

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance per flip-flop

No load

35

pF