SN54ALS137A, SN74ALS137A, SN74AS137

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

WITH ADDRESS LATCHES

SDAS203C – APRIL 1982 – REVISED JANUARY 1995

2

POST OFFICE BOX 655303

X/Y

1

A

2

B

3

C

C8

4

5

6

G1

Y0

15

0

&

EN

Y1

14

1

Y2

13

2

Y3

12

3

Y4

11

4

Y5

10

5

Y6

9

6

Y7

7

7

G

7

0

LE

G2

8D

1

2

4

DMUX

1

A

2

B

3

C

C8

4

5

6

G1

Y0

15

0

&

Y1

14

1

Y2

13

2

Y3

12

3

Y4

11

4

Y5

10

5

Y6

9

6

Y7

7

7

LE

G2

8D

0

2

† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, J, and N packages.

logic diagram (positive logic)

G1

G2

LE

C

B

A

6

5

4

3

2

1

Output

Enables

Latch

Enable

Select

Inputs

Data

Outputs

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

10

11

12

13

14

7

9

15

Pin numbers shown are for the D, J, and N packages.