SN54ACT74, SN74ACT74

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH CLEAR AND PRESET

SCAS520E – AUGUST 1995 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303

S

4

3

1CLK

1D

2

1D

R

1

1Q

5

6

C1

10

11

2CLK

12

2D

13

2Q

9

8

1PRE

2PRE

1CLR

2CLR

1Q

2Q

† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, N, PW, and W packages.

logic diagram, each flip-flop (positive logic)

C

C

C

C

C

C

C

C

TG

TG

TG

TG

Q

Q

PRE

CLK

D

CLR

C

C