8D

7D

6D

5D

4D

3D

2D

1D

CLK

CLR

18

17

14

13

8

7

4

3

11

1

1D

C1

EN

8Q

7Q

6Q

5Q

4Q

3Q

2Q

1Q

19

16

15

12

6

5

2

9

† This symbol is in accordance with ANSI/IEEE Std.

91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, J, N, and W packages.

SN54273, SN54LS273, SN74273, SN74LS273

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

SDLS090 – OCTOBER 1976 – REVISED MARCH 1988

Copyright

1

POST OFFICE BOX 655303

Outputs

Buffer/Storage Registers

Shift Registers

Pattern Generators

description

These monolithic, positive-edge-triggered flip-

flops utilize TTL circuitry to implement D-type

flip-flop logic with a direct clear input.

Information at the D inputs meeting the setup time

requirements is transferred to the Q outputs on the

positive-going edge of the clock pulse. Clock

triggering occurs at a particular voltage level and

is not directly related to the transition time of the

positive-going pulse. When the clock input is at

either the high or low level, the D input signal has

no effect ar the output.

These flip-flops are guaranteed to respond to

clock frequencies ranging form 0 to 30 megahertz

while maximum clock frequency is typically 40

megahertz. Typical power dissipation is 39

milliwatts per flip-flop for the

′273 and 10 milliwatts

for the

′LS273.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLEAR

CLOCK

D

Q

L

X

X

L

H

↑

HH

H

↑

LL

H

L

X

Q0

SN54LS273 . . . FK PACKAGE

(TOP VIEW)

SN54273, SN74LS273 ...J OR W PACKAGE

SN74273 ...N PACKAGE

SN74LS273 . . . DW OR N PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK

32

1 20 19

910 11 12 13

4

5

6

7

8

18

17

16

15

14

8D

7D

7Q

6Q

6D

2D

2Q

3Q

3D

4D

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.