PE88D Dual Frequency

PECL Clock Oscillator

April 2007

www.pletronics.com

425-776-1880

6

Mechanical:

Inches

mm

A

0.276 +_0.006

7.00 +_0.15

B

0.197 +_0.006

5.00 +_0.15

C

0.067 max

1.70 max

0.038

0.96

0.200

5.08

0.004

0.10

0.050

1.27

0.055

1.40

Contacts

:

Gold 11.8 μinches

0.3 μm minimum over

Nickel 50 to 350 μinches

1.27 to 8.89 μm

Not to Scale

0.024

0.60

0.004R

0.10R

0.008R

0.20R

Pad

Function

Note

1

Output

Enable/Disable

When this pad is not connected the oscillator shall operate.

When this pad is <0.30 volts, the output will be inhibited (high impedance state.)

Recommend connecting this pad to V

2

F Select

Logic High: 106.25 MHz, Logic Low: 212.50 MHz

3

Ground (GND)

4

Output

Both outputs must be terminated and biased for proper operation. The ideal

termination is 50 ohms connected to 2.0V below the positive Supply Voltage.

5

Output*

6

Supply Voltage

(V

Recommend connecting appropriate power supply bypass capacitors as close as

possible.

Layout and application information

For Optimum Jitter Performance, Pletronics recommends:

•

a ground plane under the device

•

no large transient signals (both current and voltage) should be routed under the device

•

do not layout near a large magnetic field such as a high frequency switching power supply

•

do not place near piezoelectric buzzers or mechanical fans.