HC1S80 datasheet(3/110 Pages) ALTERA

3 / 110 page

Altera Corporation

1–1

September 2008

Preliminary

1. Introduction to HardCopy

Stratix Devices

Introduction

HardCopy® Stratix® structured ASICs, Altera’s second-generation

HardCopy structured ASICs, are low-cost, high-performance devices

with the same architecture as the high-density Stratix FPGAs. The

combination of Stratix FPGAs for prototyping and design verification,

HardCopy Stratix devices for high-volume production, and the

Quartus® II design software beginning with version 3.0, provide a

complete and powerful alternative to ASIC design and development.

HardCopy Stratix devices are architecturally equivalent and have the

same features as the corresponding Stratix FPGA. They offer pin-to-pin

compatibility using the same package as the corresponding Stratix FPGA

prototype. Designers can prototype their design to verify functionality

with Stratix FPGAs before seamlessly migrating the proven design to a

HardCopy Stratix structured ASIC.

The Quartus II software provides a complete set of inexpensive and

easy-to-use tools for designing HardCopy Stratix devices. Using the

successful and proven methodology from HardCopy APEX™ devices,

Stratix FPGA designs can be seamlessly and quickly migrated to a

low-cost ASIC alternative. Designers can use the Quartus II software to

design HardCopy Stratix devices to obtain an average of 50% higher

performance and up to 40% lower power consumption than can be

achieved in the corresponding Stratix FPGAs. The migration process is

fully automated, requires minimal customer involvement, and takes

approximately eight weeks to deliver fully tested HardCopy Stratix

prototypes.

The HardCopy Stratix devices use the same base arrays across multiple

designs for a given device density and are customized using the top two

metal layers. The HardCopy Stratix family consists of the HC1S25,

HC1S30, HC1S40, HC1S60, and HC1S80 devices. Table 1–1 provides the

details of the HardCopy Stratix devices.

H51001-2.4

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