HC1S25 datasheet(91/110 Pages) ALTERA

91 / 110 page

Altera Corporation

6–3

September 2008

Design Guidelines for HardCopy Stratix Performance Improvement

■

Do not use tri-state signals or bidirectional ports on hierarchical

boundaries. If you use tri-state boundaries in a lower-level block,

synthesis pushes the tri-state signals through the hierarchy to the

top-level. This takes advantage of the tri-state drivers on the output

pins of the Altera device. Since this requires optimizing through

hierarchies, lower-level boundary tri-state signals are not supported

with a block-level design methodology.

■

Limit clocks to one per block. Partitioning your design into clock

domains makes synthesis and timing analysis easier.

■

Place state machines in separate blocks to speed optimization and

provide greater encoding control.

■

Separate timing-critical functions from non-timing-critical functions.

■

Limit the critical timing path to one hierarchical block. Group the

logic from several design blocks to ensure the critical path resides in

one block.

These guidelines apply to all Altera device architectures including

HardCopy Stratix devices. Partitioning functional boundaries to have all

outputs immediately registered is crucial to using LogicLock regions

effectively in HardCopy devices. With registered outputs, you allow the

signals to leave a function block at the start of the clock period. This gives

the signals more set-up time to reach their endpoints in the clock period.

In large designs that are partitioned into multiple function blocks, the

block-to-block interconnects are often the limiting factor for fMAX

performance. Registered outputs give the Quartus II Fitter the optimal

place-and-route flexibility for interconnects between major function

blocks.

Physical Synthesis Optimization

All physical synthesis settings in the Quartus II software can be used in

the HARDCOPY_FPGA_PROTOTYPE design. These settings are found

in the Physical Synthesis Optimizations section of the Fitter Settings

dialog box (Assignments menu) and include the following settings:

■

Physical synthesis for combinational logic

■

These settings can improve FPGA performance while developing the

HARDCOPY_FPGA_PROTOTYPE. All modifications are passed along

into the HardCopy Stratix project when you run the HardCopy Timing

Optimization wizard. After running the HardCopy Timing Optimization

wizard and subsequently opening the HardCopy project in the Quartus II

software, these physical synthesis optimizations are disabled. No further

modifications to the netlist are made.

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