EPF6016 datasheet(3/52 Pages) ALTERA

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Altera Corporation

FLEX 6000 Programmable Logic Device Family Data Sheet

General

Description

The Altera® FLEX 6000 programmable logic device (PLD) family provides

a low-cost alternative to high-volume gate array designs. FLEX 6000

devices are based on the OptiFLEX architecture, which minimizes die size

while maintaining high performance and routability. The devices have

reconfigurable SRAM elements, which give designers the flexibility to

quickly change their designs during prototyping and design testing.

Designers can also change functionality during operation via in-circuit

reconfiguration.

FLEX 6000 devices are reprogrammable, and they are 100

% tested prior to

shipment. As a result, designers are not required to generate test vectors

for fault coverage purposes, allowing them to focus on simulation and

design verification. In addition, the designer does not need to manage

inventories of different gate array designs. FLEX 6000 devices are

configured on the board for the specific functionality required.

Table 3 shows FLEX 6000 performance for some common designs. All

performance values shown were obtained using Synopsys DesignWare or

LPM functions. Special design techniques are not required to implement

the applications; the designer simply infers or instantiates a function in a

Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or

schematic design file.

Note:

(1)

This performance value is measured as a pin-to-pin delay.

Table 3. FLEX 6000 Device Performance for Common Designs

Application

LEs Used

Performance

Units

-1 Speed

Grade

-2 Speed

Grade

-3 Speed

Grade

16-bit loadable counter

172

153

133

MHz

16-bit accumulator

172

153

133

MHz

24-bit accumulator

136

123

108

MHz

16-to-1 multiplexer (pin-to-pin) (1)

12.1

13.4

16.6

× 16 multiplier with a 4-stage pipeline

592

MHz

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