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PCI2250 bảng dữ liệu(PDF) 51 Page - Texas Instruments |
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PCI2250 bảng dữ liệu(HTML) 51 Page - Texas Instruments |
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51 / 85 page ![]() 5–1 5 Extension Registers The TI extension registers are those registers that lie outside the standard PCI-to-PCI bridge device configuration space (i.e., registers 40h–FFh in PCI configuration space in the PCI2250). These registers can be accessed through configuration reads and writes. The TI extension registers add flexibility and performance benefits to the standard PCI-to-PCI bridge. The TI extension registers are not reset on the transition from D3 to D0. 5.1 Chip Control Register The chip control register is read/write and has a default value of 00h. This register is used to control the functionality of certain PCI transactions. See Table 5–1 for a complete description of the register contents. Bit 7 6 5 4 3 2 1 0 Name Chip control Type R R R R/W R R R/W R Default 0 0 0 0 0 0 0 0 Register: Chip control Type: Read/Write, Read–only Offset: 40h Default: 00h Table 5–1. Chip Control Register BIT TYPE FUNCTION 7–5 R Reserved. Bits 7–5 return 0s when read. 4 R/W Memory read prefetch. When cleared, bit 4 enables the memory read prefetch. 0 = Upstream memory reads are enabled (default) 1 = Upstream memory reads are disabled 3–2 R Reserved. Bits 3 and 2 return 0s when read. 1 R/W Reserved 0 R Reserved. Bit 0 returns 0 when read. |
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