PCI2040 datasheet(21/79 Pages) TI

21 / 79 page

3–1

3 PCI2040 Functional Description

This section covers the functional description for PCI2040. The PCI2040 provides a 32-bit PCI host interface and an

interface for 8-bit and 16-bit host port interface (HPI) ports for TI’s C54x and C6x families of DSP processors. The

following conventions are used in this document:

•

DSP

C54x or C6x

•

Word

16 bits for PCI, 16 bits for C54x, 32 bits for C6x

•

Half-word

8 bits for C54x, 16 bits for C6x

•

Double-word

32 bits for PCI

Figure 3–1 shows a simplified block diagram of the PCI2040.

PCI Host Bus Interface

Miscellaneous

Interface

CPCI Hot-Swap

PCI Power

Management

Serial ROM

GPIO

Interrupt

PCI

Target

HPI

Interface

Registers

PCI

Registers

C6x

Host

Port

Extensions

C54x

Host

Port

HPI Interface

GP BUS

Interface

Figure 3–1. PCI2040 System Block Diagram

3.1

PCI Interface

PCI2040 provides an integrated 32-bit PCI bus interface compliant with the

PCI Local Bus Specification. The PCI2040

incorporates a PCI target interface for configuration cycles, accesses to internal registers, and access to the HPI

interface via memory-mapped space. The PCI2040 does not provide PCI mastering.

As a PCI bus target, PCI2040 incorporates the following features:

•

Supports the memory read, memory write, configuration read, and configuration write

•

Aliases the memory read multiple, memory read line, and memory write and invalidate to the basic

memory commands (i.e., memory read and memory write)

•

Supports PCI_LOCK

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