PCI1451 datasheet(51/141 Pages) TI

51 / 141 page

3–19

•

Card control register (PCI offset 91h): bits 7, 6, 2, 1, 0

•

Device control register (PCI offset 92h): bits 7–0

•

Diagnostic register (PCI offset 93h): bits 7–0

•

Socket DMA register 0 (PCI offset 94h): bits 1–0

•

Socket DMA register 1 (PCI offset 98h): bits 15–0

•

GPE control/status register (PCI offset A8h): bits 10, 9, 8, 2, 1, 0

PME context bits

•

Bridge control register (PCI offset 3Eh): bit 6

•

Power management capabilities register (PCI offset A2h): bit 15

•

Power management control/status register (PCI offset A4h): bits 15, 8

•

ExCA power control register (ExCA 802h/842h): bits 7, 4, 3, 1, 0

•

ExCA interrupt and general control (ExCA 803h/843h): bit 6, 5

•

ExCA card status change register (ExCA 804h/844h): bits 3–0

•

ExCA card status change interrupt register (ExCA 805h/845h): bits 3–0

•

CardBus socket event register (CardBus offset 00h): bits 3–0

•

CardBus socket mask register (CardBus offset 04h): bits 3–0

•

CardBus socket control register (CardBus offset 10h): bits 6, 5, 4, 2, 1, 0

3.6.6

System Diagram Implementing CardBus Device Class Power Management

PCI1451

South Bridge

Embedded

Controller

PME

PC Card

Socket A

TPS2206

Power

Switch

PC Card

Socket B

CLKRUN

PCI Bus

Clock

PRST

GRST†

Vcc

System Vcc

Vaux

Make before

break switch

D3Status

Real Time

Clock‡

† The system connection to GRST is implementation specific. GRST should be applied whenever Vcc is applied to the PCI1451. PRST should be

applied for subsequent warm resets.

‡ Not required if internal oscillator is used.

Figure 3–15. System Diagram Implementing CardBus Device Class Power Management

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