PCI1420 datasheet(21/137 Pages) TI

21 / 137 page

2–9

Table 2–7. PCI System

TERMINAL

NAME

NO.

I/O

DESCRIPTION

NAME

PDV

GHK

GRST

175

A11

Global reset. When the global reset is asserted, the GRST signal causes the PCI1420 to place all output

buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is

completely in its default state. For systems that require wake-up from D3, GRST will normally be asserted

only during initial boot. PRST should be asserted following initial boot so that PME context is retained when

transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST should be tied to PRST.

When the SUSPEND mode is enabled, the device is protected from the GRST, and the internal registers are

preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

PCLK

180

A10

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the

rising edge of PCLK.

PRST

166

A14

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1420 to place all output buffers in a

high-impedance state and reset internal registers. When PRST is asserted, the device is completely

nonfunctional. After PRST is deasserted, the PCI1420 is in a default state.

When the SUSPEND mode is enabled, the device is protected from the PRST, and the internal registers are

preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

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