MAX3238

3V TO 5.5V MULTICHANNEL RS232 LINE DRIVER/RECEIVER

WITH ±15kV ESD (HBM) PROTECTION

SLLS349J − JUNE 1999 − REVISED MARCH 2004

8

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

50

Ω

TEST CIRCUIT

VOLTAGE WAVEFORMS

0 V

3 V

Output

Input

VOL

VOH

tPLH

Generator

(see Note B)

RL

3 V

FORCEOFF

RS-232

Output

tPHL

CL

(see Note A)

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

50%

50%

1.5 V

1.5 V

Figure 2. Driver Pulse Skew

TEST CIRCUIT

VOLTAGE WAVEFORMS

50

Ω

−3 V

3 V

Output

Input

VOL

VOH

tPHL

Generator

(see Note B)

tPLH

Output

CL

(see Note A)

3 V or 0 V

FORCEON

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

3 V

FORCEOFF

1.5 V

1.5 V

50%

50%

Figure 3. Receiver Propagation Delay Times

TEST CIRCUIT

50

Ω

Generator

(see Note B)

3 V or 0 V

3 V or 0 V

FORCEON

FORCEOFF

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

C. tPLZ and tPHZ are the same as tdis.

D. tPZL and tPZH are the same as ten.

RL

S1

VCC

GND

CL

(see Note A)

Output

VOLTAGE WAVEFORMS

Output

VOL

VOH

3 V

0 V

0.3 V

Output

Input

0.3 V

1.5 V

1.5 V

50%

tPHZ

(S1 at GND)

tPLZ

(S1 at VCC)

50%

tPZL

(S1 at VCC)

Figure 4. Receiver Enable and Disable Times