8-Bit Registered Transceiver

CY74FCT652T

SCCS032 - September 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modified to remove devices not offered.

Copyright

Features

• Function, pinout, and drive compatible with FCT and

F logic

• FCT-C speed at 5.4 ns max. (Com’l)

FCT-A speed at 6.3 ns max. (Com’l)

FCT functions

• Edge-rate control circuitry for significantly improved

noise characteristics

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• Sink Current

64 mA

Source Current

32 mA

• Independent register for A and B buses

• Multiplexed real-time and stored data transfer

• Extended commercial range of

−40˚C to +85˚C

Functional Description

The FCT652T consists of bus transceiver circuits, D-type

flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the input bus or from the

internal storage registers. GAB and GBA control pins are

provided to control the transceiver functions. SAB and SBA

control pins are provided to select either real-time or stored

data transfer. The circuitry used for select control will eliminate

the typical decoding glitch that occurs in a multiplexer during

the transition between stored and real-time data. A LOW input

level selects real-time data and a HIGH selects stored data.

Data on the A or B data bus, or both, can be stored in the

internal D flip-flops by LOW-to-HIGH transitions at the

appropriate clock pins (CPAB or CPBA), regardless of the

select or enable control pins. When SAB and SBA are in the

real-time transfer mode, it is also possible to store data without

using the internal D-type flip-flops by simultaneously enabling

GAB and GBA. In this configuration, each output reinforces its

input. Thus, when all other data sources to the two sets of bus

lines are at high impedance, each set of bus lines will remain

at its last state.

The outputs are designed with a power-off disable feature to

allow for live insertion of boards.

Logic Block Diagram

Pin Configurations

C

D

28

4

5

6

7

8

9

10

3

2

1

27

13

14

15

16

17

26

25

24

23

22

21

20

11

12

19

18

LCC

Top View

C

D

TO 7 OTHER CHANNELS

CPAB

SAB

SBA

GBA

GAB

CPBA

SAB

SBA

CPAB

NC

GAB

CPBA

B REG

A REG

1OF 8 CHANNELS

NC

GND

1

2

3

4

5

6

7

8

9

10

11

12

16

17

18

19

20

24

23

22

21

13

14

15

Top View

CPAB

CPBA

SAB

SBA

GAB

GBA

GND

SOIC/QSOP