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CDC586 bảng dữ liệu(PDF) 3 Page - Texas Instruments

tên linh kiện CDC586
Giải thích chi tiết về linh kiện  3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
PDF  12 Pages
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CDC586 bảng dữ liệu(HTML) 3 Page - Texas Instruments

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CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998
3
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
output configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate
at the same frequency as CLKIN.
Table 1. Output Configuration A
INPUTS
OUTPUTS
SEL1
SEL0
1/2x
FREQUENCY
1x
FREQUENCY
L
L
None
All
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B
INPUTS
OUTPUTS
SEL1
SEL0
1x
FREQUENCY
2x
FREQUENCY
L
L
All
None
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H
1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3



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