CDC2586

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998

2

POST OFFICE BOX 655303

description (continued)

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs

(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN

frequency depending on which output is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles

are adjusted to 50% independent of the duty cycle at CLKIN.

Output-enable (OE) provides output control. When OE is high, the outputs are in the high-impedance state.

When OE is low, the outputs are active. TEST is used for factory testing of the device and can be used to bypass

the PLL. TEST should be strapped to GND for normal operation.

Unlike many products containing PLLs, the CDC2586 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2586 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application

of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or

feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST, and upon

enable of all outputs via OE.

The CDC2586 is characterized for operation from 0

°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2586 PLL has a frequency range of 100 MHz to

200 MHz, twice the operating frequency range of the CDC2586 outputs. The output of the VCO is divided by

two and four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO

frequency. The SEL0 and SEL1 inputs select which of the two signals are buffered to each bank of device

outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the

frequency and phase of this output matches that of the CLKIN signal. In the case that a VCO/2 output is wired

to FBIN, the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either

the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at

twice or the same as the CLKIN frequency.