FD7T datasheet(11/19 Pages) PLETRONICS

11 / 19 page

FD7T Series Multi-Output

CMOS Clock Oscillator

May 2008

www.pletronics.com

425-776-1880

10 30 50 70 90 110 130 150 170 190 210 230

Fout (MHz)

10 30 50 70 90 110 130 150 170 190 210 230

Fout (MHz)

7 Outputs On

6 Outputs On

5 Outputs On

4 Outputs On

3 Outputs On

2 Outputs On

1 Output On

All outputs Off

90 110 130 150 170 190 210 230

Fout (MHz)

7 Outputs On

6 Outputs On

5 Outputs On

4 Outputs On

3 Outputs On

2 Outputs On

1 Output On

All outputs Off

90 110 130 150 170 190 210 230

Fout (MHz)

90 110 130 150 170 190 210 230

PLL Frequency (MHz)

4 PLLs On

3 PLLs On

2 PLLs On

1 PLL On

All PLLs Off

FD7xxxT

DDOUT Current for Various Number of Outputs On

No Load

VDD=1.8V

DDOUT=3.3V

DDOUT=2.5V

DDOUT=1.8V

FD7xxxTL V

DD = VDDOUT=1.8V

FD7 Series I

DD versus PLLs Used

No Load

DD=1.8V

Phase noise of the reference signal, Out1.

25MHz Reference Frequency

RMS jitter is 1.4pS from 10Hz to 2MHz

Example of the PLL synthesizing a frequency.

25MHz Reference Frequency

Multiply by 8 to 200MHz

Divide the 200MHz PLL output by 8

Phase noise plot of the resulting 25MHz on Out 2

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