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LTC3220IPF-PBF bảng dữ liệu(PDF) 4 Page - Linear Technology |
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LTC3220IPF-PBF bảng dữ liệu(HTML) 4 Page - Linear Technology |
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4 / 20 page ![]() LTC3220/LTC3220-1 4 32201fb TYPICAL PERFORMANCE CHARACTERISTICS Mode Switch Dropout Times 1.5x Mode CPO Ripple 2x Mode CPO Ripple Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Based on long term current density limitations. Note 3: The LTC3220E/LTC3220E-1 are guaranteed to meet performance specifications from 0°C to 85°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTC3220I/LTC3220I-1 are guaranteed to meet performance specifications over the full –40°C to 125°C operating temperature range. TA = 25°C unless otherwise noted. Note 4: These devices include overtemperature protection that is intended to protect the devices during momentary overload conditions. Junction temperatures will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. Note 5: 1.5x mode output impedance is defined as (1.5VIN – VCPO)/IOUT. 2x mode output impedance is defined as (2VIN – VCPO)/IOUT. Note 6: All values are referenced to VIH and VIL levels. Note 7: Guaranteed by design. VCPO 1V/DIV VIN = 3.6V 250μs/DIV 3220 G01 1 1.5 2 VCPO 20mV/DIV AC COUPLED VIN = 3.6V ICPO = 200mA CCPO = 4.7μF 500ns/DIV 3220 G02 VCPO 20mV/DIV AC COUPLED VIN = 3.6V ICPO = 200mA CCPO = 4.7μF 500ns/DIV 3220 G03 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, DVCC = 3V, RST = high, C1 = C2 = C3 = 2.2μF, C4 = 4.7μF, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tHD,DAT(OUT) Data Hold Time 0 900 ns tHD,DAT(IN) Input Data Hold Time 0 ns tSU,DAT Data Setup Time 100 ns tLOW Clock Low Period 1.3 μs tHIGH Clock High Period 0.6 μs tf Clock Data Fall Time 20 300 ns tr Clock Data Rise Time 20 300 ns tSP Spike Supression Time 50 ns |
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