LTC2483CDD datasheet(12/32 Pages) LINER

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LTC2483

2483f

SDA

SCL

SSr

tLOW

tHD;STA

tBUF

tSP

tSU;STA

tSU;STO

tHD;DAT

tHIGH

tSU;DAT

2483 F02

APPLICATIO S I FOR ATIO

Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus

The START and STOP Conditions

A START condition is generated by transitioning SDA from

HIGH to LOW while SCL is HIGH. The bus is considered to

be busy after the START condition. When the data transfer

is finished, a STOP condition is generated by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus is free

again a certain time after the STOP condition. START and

STOP conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The

repeated START (Sr) conditions are functionally identical

to the START (S).

Data Transferring

After the START condition, the I2C bus is busy and data

transfer is set between a master and a slave. Data is

transferred over I2C in groups of nine bits (one byte)

followed by an acknowledge bit, therefore each group

takes nine SCL cycles. The transmitter releases the SDA

line during the acknowledge clock pulse and the receiver

issues an Acknowledge (ACK) by pulling SDA LOW or

leaves SDA HIGH to indicate a Not Acknowledge (NAK)

condition. Change of data state can only happen while SCL

is LOW.

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