LTC2248/LTC2247/LTC2246

23

224876fa

APPLICATIO S I FOR ATIO

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

5.00

± 0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE

M0-220 VARIATION WHHD-(X) (TO BE APPROVED)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE

DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT,

SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40

± 0.10

0.23 TYP

(4 SIDES)

31

1

2

32

BOTTOM VIEW—EXPOSED PAD

3.45

± 0.10

(4-SIDES)

0.75

± 0.05

R = 0.115

TYP

0.25

± 0.05

(UH) QFN 0603

0.50 BSC

0.200 REF

0.00 – 0.05

0.70

±0.05

3.45

±0.05

(4 SIDES)

4.10

±0.05

5.50

±0.05

0.25

± 0.05

PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT

UH Package

32-Lead Plastic QFN (5mm

× 5mm)

(Reference LTC DWG # 05-08-1693)

PACKAGE DESCRIPTIO

Bottomside

Silkscreen Bottom