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LTC1867LIGN bảng dữ liệu(PDF) 4 Page - Linear Technology

tên linh kiện LTC1867LIGN
Giải thích chi tiết về linh kiện  Micropower, 3V, 12-/16-Bit, 8-Channel 175ksps ADCs
PDF  16 Pages
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nhà sản xuất  LINER [Linear Technology]
Trang chủ  http://www.linear.com
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LTC1867LIGN bảng dữ liệu(HTML) 4 Page - Linear Technology

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LTC1863L/LTC1867L
4
1863L7Lf
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
Supply Voltage
(Note 9)
2.7
3.6
V
IDD
Supply Current
fSAMPLE = 175ksps, Internal REF
●
0.75
1
mA
NAP Mode
170
µA
SLEEP Mode
●
0.2
3
µA
PDISS
Power Dissipation
fSAMPLE = 175ksps
●
2
2.7
mW
TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE
Maximum Sampling Frequency
●
175
kHz
tCONV
Conversion Time
●
3.2
3.7
µs
tACQ
Acquisition Time
●
2.01
1.68
µs
fSCK
SCK Frequency
20
MHz
t1
CS/CONV High Time
Short CS/CONV Pulse Mode
●
40
100
ns
t2
SDO Valid After SCK↓
CL = 25pF (Note 11)
●
22
47
ns
t3
SDO Valid Hold Time After SCK↓
CL = 25pF
●
517
ns
t4
SDO Valid After CS/CONV↓
CL = 25pF
●
20
40
ns
t5
SDI Setup Time Before SCK↑
●
15
–6
ns
t6
SDI Hold Time After SCK↑
●
15
6
ns
t7
SLEEP Mode Wake-Up Time
CREFCOMP = 10µF, CVREF = 2.2µF80
ms
t8
Bus Relinquish Time After CS/CONV↑
CL = 25pF
●
30
50
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to GND (unless otherwise
noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
greater than 100mA below GND without latchup. These pins are not
clamped to VDD.
Note 5: VDD = 2.7V, fSAMPLE = 175ksps and fSCK = 20MHz at 25°C,
tr = tf = 5ns and VIN– = 1.25V for bipolar mode unless otherwise specified.
Note 6: Linearity, offset and gain error specifications apply for both
unipolar and bipolar modes. The INL and DNL are tested in bipolar mode.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Unipolar offset is the offset voltage measured from +1/2LSB
when the output code flickers between 0000 0000 0000 0000 and
0000 0000 0000 0001 for LTC1867L and between 0000 0000 0000 and
0000 0000 0001 for LTC1863L. Bipolar offset is the offset voltage
measured from –1/2LSB when output code flickers between 0000 0000
0000 0000 and 1111 1111 1111 1111 for LTC1867L, and between
0000 0000 0000 and 1111 1111 1111 for LTC1863L.
Note 9: Recommended operating conditions. The input range of ±1.25V
for bipolar mode is measured with respect to VIN
– = 1.25V. For unipolar
mode, common mode input range is 0V to VDD for the positive input and
0V to 1.5V for the negative input. For bipolar mode, common mode input
range is 0V to VDD for both positive and negative inputs.
Note 10: Guaranteed by design, not subject to test.
Note 11: t2 of 47ns maximum allows fSCK up to 10MHz for rising capture
with 50% duty cycle and fSCK up to 20MHz for falling capture (with 3ns
setup time for the receiving logic).
POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC1863L/LTC1867L/LTC1867LA
LTC1863L/LTC1867L/LTC1867LA



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