LTM4603 datasheet(13/24 Pages) LINER

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LTM4603/LTM4603-1

4603f

APPLICATIO S I FOR ATIO

the ramp of the internal reference and the output voltage.

The total soft-start time can be calculated as:

V V

SOFTSTART

OUT MARGIN

()

.•

.–

•

()

When the RUN pin falls below 1.5V, then the SS pin is reset

to allow for proper soft-start control when the regulator

is enabled again. Current foldback and force continuous

mode are disabled during the soft-start process. The

soft-start function can also be used to control the output

ramp up time, so that another regulator can be easily

tracked to it.

Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TRACK/SS pin. The output can be tracked up and

down with another regulator. The master regulator’s output

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider. Figure 5

shows an example of coincident tracking. Ratiometric

modes of tracking can be achieved by selecting different

resistor values to change the output tracking ratio. The

master output must be greater than the slave output for

the tracking to work. Figure 6 shows the coincident output

tracking characteristics.

Run Enable

The RUN pin is used to enable the power module. The

pin has an internal 5.1V zener to ground. The pin can be

driven with a logic input not to exceed 5V.

The RUN pin can also be used as an undervoltage lock out

(UVLO) function by connecting a resistor divider from the

input supply to the RUN pin:

UVLO =

•.

Power Good

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a ±10% window around the regulation point and tracks

with margining.

COMP Pin

This pin is the external compensation pin. The module

has already been internally compensated for most output

voltages. Table 2 is provided for most application require-

ments. A spice model will be provided for other control

loop optimization.

PLLIN

The power module has a phase-locked loop comprised of an

internal voltage controlled oscillator and a phase detector.

This allows the internal top MOSFET turn-on to be locked

Figure 5

Figure 6

VOUT

VFB

MARG0

MARG1

VOUT_LCL

DIFFVOUT

VOSNS

–

PGOOD

MPGM

RUN

COMP

INTVCC

DRVCC

TRACK/SS

TRACK CONTROL

PLLIN

LTM4603

RSET

40.2k

100k

40.2k

MASTER

OUTPUT

60.4k

COUT

SLAVE OUTPUT

4603 F05

60.4k FROM

VOUT TO VFB

CIN

VIN

fSET

PGND

SGND

VIN

OUTPUT

VOLTAGE

TIME

4603 F06

MASTER OUTPUT

SLAVE OUTPUT

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