LTC1860CS8 datasheet(12/16 Pages) LINER

12 / 16 page

LTC1860/LTC1861

18601fa

APPLICATIONS INFORMATION

LTC1861 OPERATION

Operating Sequence

The LTC1861 conversion cycle begins with the rising edge

of CONV. After a period equal to tCONV, the conversion is

ﬁnished. If CONV is left high after this time, the LTC1861

goes into sleep mode. The LTC1861’s 2-bit data word is

clocked into the SDI input on the rising edge of SCK after

CONV goes low. Additional inputs on the SDI pin are then

ignored until the next CONV cycle. The shift clock (SCK)

synchronizes the data transfer with each bit being trans-

mitted on the falling SCK edge and captured on the rising

SCK edge in both transmitting and receiving systems.

The data is transmitted and received simultaneously (full

duplex). After completing the data transfer, if further SCK

clocks are applied with CONV low, SDO will output zeros

indeﬁnitely. See Figure 4.

Analog Inputs

The two bits of the input word (SDI) assign the MUX

conﬁguration for the next requested conversion. For a

given channel selection, the converter will measure the

voltage between the two channels indicated by the “+”

and “–” signs in the selected row of the following table. In

single-ended mode, all input channels are measured with

respect to GND (or AGND). A zero code will occur when

the “+” input minus the “–” input equals zero. Full scale

occurs when the “+” input minus the “–” input equals

VREF minus 1LSB. See Figure 5. Both the “+” and “–”

inputs are sampled at the same time so common mode

noise is rejected. The input span in the SO-8 package is

ﬁxed at VREF = VCC. If the “–” input in differential mode

is grounded, a rail-to-rail input span will result on the

“+” input.

Figure 4. LTC1861 Operating Sequence

Figure 5. LTC1861 Transfer Curve

CONV

SDI

SCK

SDO

B11 B10

B0*

Hi-Z

S/D O/S

DON’T CARE

tCONV

1860 F04

SLEEP MODE

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE

APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

Hi-Z

tSMPL

VIN*

*VIN = (SELECTED “+” CHANNEL) –

(SELECTED “–” CHANNEL)

REFER TO TABLE 1

0 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 0

•

1860 F05

MUX ADDRESS

Table 1. Multiplexer Channel Selection

SGL/DIFF

ODD/SIGN

CHANNEL #

–

GND

–

186465 TBL1

SINGLE-ENDED

MUX MODE

DIFFERENTIAL

MUX MODE

LTC1860CS8 bảng dữ liệu(PDF) 12 Page - Linear Technology

LTC1860CS8 bảng dữ liệu(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bảng dữ liệu tải về

Link URL