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LTC1642AIGN bảng dữ liệu(PDF) 14 Page - Linear Technology

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Trang chủ  http://www.linear.com
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LTC1642AIGN bảng dữ liệu(HTML) 14 Page - Linear Technology

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LTC1642A
1642af
APPLICATIO S I FOR ATIO
The undervoltage monitor behaves differently if FB is
above its threshold when the GATE begins ramping:
RESET goes high as soon as the GATE ramp begins.
RESET goes low immediately if VCC falls below the chip’s
2.5V internal undervoltage lockout threshold.
To disable the undervoltage monitor, tie FB to REF and
ground RESET.
D1
1N4705
18V
GATE
ON
14
SENSE
15
FB
7
RESET
5
4
VCC
16
R2
0.015
Ω
Q1
FDS6630A
GND
LTC1642A
8
RST TMR
3
1642a F12
R3
100
Ω
R4
330
Ω
C2
0.047
µF
R9
95.3k
1%
R8
12.4k
1%
+
C1
0.33
µF
ALL RESISTORS
±5% UNLESS NOTED.
FB COMPARATOR TRIPS AT VOUT = 10.7V
VIN
12V
2.5A
VOUT
CLOAD
Figure 12. Undervoltage Monitoring Circuitry
Figure 13. Supply Monitor Waveforms
REFERENCE CURRENT
100
µA
1mA
10mA
1642a F14
0.1
0.2
0.4
1.0
2.0
4.0
10.0
Figure 14. Minimum REF Compensation vs REF Current
Reference
The LTC1642A’s internal voltage reference is buffered and
brought out to the REF pin. The buffer amplifier should be
compensated with a capacitor connected between REF
and ground. If no DC current is drawn from REF, 0.1
µF
ensures an adequate phase margin, but the minimum
compensation increases if REF sources a substantial DC
current, as shown in Figure 14.
t1
t2 t3
t4
t5
250ms/DIV
1642a F13
VIN
20V/DIV
VRSTTMR
1V/DIV
VRESET
10V/DIV



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