LTC1400CS8 datasheet(13/20 Pages) LINER

13 / 20 page

LTC1400

1400fa

APPLICATIO S I FOR ATIO

In the Sleep mode, power consumption is reduced to a

minimum by cutting off the supply to all internal circuitry

includingthereference.Figure12showsthewaystopower

down the LTC1400. The chip can enter the Nap mode by

keeping the CLK signal low and pulsing the CONV signal

twice. For Sleep mode operation, CONV signal should be

pulsed four times while CLK is kept low.

The LTC1400 can be returned to active mode easily. The

rising edge of CLK will wake-up the LTC1400. During the

transition from Sleep mode to active mode, the VREF volt-

age ramp-up time is a function of the loading conditions.

With a 10μF bypass capacitor, the wake-up time from

Sleep mode is typically 4ms. A REFRDY signal will be

activated once the reference has settled and is ready for

an A/D conversion. This REFRDY bit is output to the DOUT

pin before the rest of the A/D converted code.

Digital Interface

The digital interface requires only three digital lines. CLK

and CONV are both inputs, and the DOUT output provides

the conversion result in serial form.

Figure 13 shows the digital timing diagram of the LTC1400

during the A/D conversion. The CONV rising edge starts

the conversion. Once initiated, it can not be restarted until

the conversion is completed. If the time from CONV signal

to CLK rising edge is less than t2, the digital output will

be delayed by one clock cycle.

The digital output data is updated on the rising edge of the

CLK line. DOUT data should be captured by the receiving

system on the rising CLK edge. Data remains valid for a

minimum time of t10 after the rising CLK edge to allow

capture to occur.

CLK

CONV

INTERNAL

S/H STATUS

DOUT

tACQ

SAMPLE

HOLD

Hi-Z

tCONV

tSAMPLE

1400 F13

REFRDY D11

D10

REFRDY

Figure 13. ADC Digital Timing Diagram

Figure 14. CLK to DOUT Delay

t10

VIH

VOH

VOL

DOUT

CLK

VIH

90%

10%

DOUT

CLK

1400 F14

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