AX2000-1CSG896PP datasheet(100/226 Pages) ACTEL

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Axcelerator Family FPGAs

2- 86

v2.7

Figure 2-68 • FIFO Read Timing

Table 2-97 • One FIFO Block

Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70°C

'–2' Speed

'–1' Speed

'Std' Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

FIFO Module Timing

tWSU

Write Setup

1.08

1.23

1.45

tWHD

Write Hold

0.22

0.25

0.30

tWCKH

WCLK High

0.98

1.11

1.31

tWCKL

WCLK Low

1.15

1.30

1.53

tWCKP

Minimum WCLK Period

2.3

2.6

3.06

tRSU

Read Setup

0.81

0.92

1.08

tRHD

Read Hold

0.00

tRCKH

RCLK High

1.00

1.14

1.34

tRCKL

RCLK Low

1.21

1.38

1.62

tRCKP

Minimum RCLK period

2.42

2.76

3.24

tCLRHF

Clear High

1.08

1.23

1.45

tCLR2FF

Clear-to-flag (EMPTY/FULL)

2.02

2.3

2.7

tCLR2AF

Clear-to-flag (AEMPTY/AFULL)

4.62

5.26

6.19

tCK2FF

Clock-to-flag (EMPTY/FULL)

2.24

2.55

tCK2AF

Clock-to-flag (AEMPTY/AFULL)

5.31

6.05

7.11

tRCK2RD1

RCLK-To-OUT (Pipelined)

1.39

1.59

1.86

tRCK2RD2

RCLK-To-OUT (Non-Pipelined)

2.62

2.98

3.5

RCLK

CLR

tRCKP

tRSU

tRHD

tRCK2RD1

tRCK2RD2

tCK2xF

tCLR2xF

tCLRHF

tRCKH

tRCKL

FREN

EMPTY, AEMPTY, AFULL, FULL

RD <35:0>

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