AX2000-1CGG896 datasheet(29/226 Pages) ACTEL

29 / 226 page

Axcelerator Family FPGAs

v2.7

2-15

activated by default to ensure a zero hold-time.

The default setting for this property can be set in

Designer. When the input buffer does not drive a

provide higher performance. Again, this can be

overridden by changing the default setting for this

property in Designer.

•

The slew-rate value for the LVTTL output buffer

can be programmed and can be set to either slow

or fast.

•

The drive strength value for LVTTL output buffers

can be programmed as well. There are four

different drive strength values – 8mA, 12mA,

16mA, or 24mA – that can be specified in

Designer.5

Using the Differential I/O Standards

Differential I/O macros should be instantiated in the

netlist. The settings for these I/O standards cannot be

changed inside Designer. Please note that there are no

tristated or bidirectional I/O buffers for differential

standards.

Using the Voltage-Referenced I/O Standards

Using these I/O standards is similar to that of single-

ended I/O standards. Their settings can be changed in

Designer.

Using DDR (Double Data Rate)

In Double Data Rate mode, new data is present on every

transition of the clock signal. Clock and data lines have

identical bandwidth and signal integrity requirements,

making it very efficient for implementing very high-

speed systems.

To implement a DDR, users need to:

1. Instantiate an input buffer (with the required I/O

standard)

2. Instantiate the DDR_REG macro (Figure 2-6)

3. Connect the output from the Input buffer to the

input of the DDR macro

Macros for Specific I/O Standards

There are different macro types for any I/O standard or

feature that determine the required VCCI and VREF

voltages for an I/O. The generic buffer macros require

the LVTTL standard with slow slew rate and 24mA-drive

strength. LVTTL can support high slew rate but this

should only be used for critical signals.

Most of the macro symbols represent variations of the six

generic symbol types:

•

CLKBUF: Clock Buffer

•

HCLKBUF: Hardwired Clock Buffer

•

INBUF: Input Buffer

•

OUTBUF: Output Buffer

•

TRIBUF: Tristate Buffer

•

BIBUF: Bidirectional Buffer

Other macros include the following:

•

Differential I/O standard macros: The LVDS and

LVPECL macros either have a pair of differential

Table 2-14 • Bank-Wide Delay Values

Bits Setting

Delay (ns)

Bits Setting

Delay (ns)

0.54

2.01

0.65

2.13

0.71

2.19

0.83

2.3

0.9

2.38

1.01

2.49

1.08

2.55

1.19

2.67

1.27

2.75

1.39

2.87

1.45

2.93

1.56

3.04

1.64

3.12

1.75

3.23

1.81

3.29

1.93

3.41

Note: Delay values are approximate and will vary with process,

temperature, and voltage.

5. These values are minimum drive strengths.

Figure 2-6 • DDR Register

DQR

CLR

PSET

CLK

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