MC-ACT-UARTM-NET datasheet(8/9 Pages) ACTEL

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WRITE TIMING

The ﬁgure below shows the setup and hold times required for a successful write. Write data is captured with the rising edge of wr_n and is written to the appropriate

location within the UARTM within the recovery time. Read or write accesses during the recovery time is not permitted. The recovery time is relaxed during back to

back write cycles to the TX FIFO.

Figure 4: Asynchronous Timing For Writes

Description

Min

Max

tWR

wr_n strobe width

2*tCY

tSUD

Setup time for D with respect to rising edge of wr_n

tCY

tSUCS

Setup time for cs_n with respect to falling edge of wr_n

tCY

tSUA

Setup time for A with respect to falling edge of wr_n

tCY

tHD

Hold time for data_in with respect to rising edge of wr_n

tCY

tHA

Hold time for A with respect to rising edge of wr_n

NUM_CHANNELS*tCY

tHCS

Hold time for cs_n with respect to rising edge of wr_n

tCY

trecovery1

Delay from previous rd_n or wr_n rising edge to the falling edge of wr_n (3*NUM_CHANNELS+3)*tCY

Table 4: Write Timing Descriptions

Where:

• tCY is the period of the system clock

• 1 A Write FIFO followed by a Write FIFO of the same channel requires a recovery time (trecovery) of a minimum of 4*tCY.

RESET TIMING

After initiating a reset to the core, allow a minimum of (8 * NUM_CHANNELS+3)*tCY after the trailing edge of reset prior to using the device. This delay is needed for

the synchronous clearing of state in each of the channels. The reset pulse with should be greater than tCY wide.

cs_n

wr_n

data_in

Data Valid

t SUD

t HD

t SUCS

t SUA

t HA

t HCS

t WR

rd_n

t recovery 1

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