LTC7652 datasheet(6/24 Pages) LINER

6 / 24 page

LTC1052/LTC7652

1052fa

50µV

10µV

5µV

Response Time vs Overdrive

VREF + OVERDRIVE

20ms/DIV

TYPICAL PERFOR A CE CHARACTERISTICS

OUTPUT

–5V

VREF – 1mV

INPUT

{

Electrical Characteristics Test Circuit (TC1)

DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)

THEORY OF OPERATIO

DC OPERATION

The shaded portion of the LTC1052 block diagram

(Figure 1a) entirely determines the amplifier’s DC

characteristics. During the auto zero portion of the cycle,

the gm1 inputs are shorted together and a feedback path is

closed around the input stage to null its offset. Switch S2

and capacitor CEXTA act as a sample-and-hold to store the

nulling voltage during the next step—the sampling cycle.

In the sampling cycle, the zeroed amplifier is used to

amplify the differential input voltage. Switch S2 connects

the amplified input voltage to CEXTB and the output gain

stage. CEXTB and S2 act as a sample-and-hold to store the

amplified input signal during the auto zero cycle.

By switching between these two states at a frequency

much higher than the signal frequency, a continuous

output results.

Notice that during the auto zero cycle the gm1 inputs are

not only shorted together, but are also shorted to the

inverting input. This forces nulling with the common mode

voltage present and accounts for the extremely high

CMRR of the LTC1052. In the same fashion, variations in

0.1µF

V–

V+

–

LTC1052

LTC1052/7652 • TC01

OUTPUT

TEST CIRCUITS

0.1µF

V–

V+

–

LTC1052

LTC1052/7652 • TC02

OUTPUT

(NOISE x 20,000)

34k

–

LT1001

34k

BANDWIDTH

10Hz

1Hz

16.2Ω

162k

16.2k

162k

16.2k

162k

0.1µF

1.0µF

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