LTC1041

4

1041fa

APPLICATIO S I FOR ATIO

The LTC1041 uses sampled data techniques to achieve

its unique characteristics. It consists of two comparators,

each of which has two differential inputs (Figure 1a).

When the sum of the voltages on a comparator’s inputs is

positive, the output is high and when the sum is negative,

the output is low. The inputs are interconnected such that

hysteresis loop of 2 • DELTA centered around the

SET POINT. (See Figure 1b.)

The dual differential input structure is made with CMOS

switches and a precision capacitor array. Input

impedance characteristics of the LTC1041 can be

determined from the equivalent circuit shown in Figure 2.

The input capacitance will charge with a time constant of

vs Load Current

0

0.8

0.4

0

8

LTC1041 • TPC06

1.2

1.6

2.0

0.6

0.2

1.0

1.4

1.8

2

1

4

3

67

9

5

10

1

10

LTC1041 • TPC07

TYPICAL PERFOR A CE CHARACTERISTICS

LTC1041 • AI01a

OSC

(6)

GND

(4)

DELTA

(5)

SET POINT

(3)

(2)

POWER ON

(7)

(8)

ON/OFF

(1)

80

µs

4

–

–

+

+

COMP B

4

TIMING

GENERATOR

CIRCUIT

–

–

+

+

COMP A

(a)

LTC1041 • AI01b

GND

0V

SET POINT

DEADBAND

Figure 1. LTC1041 Block Diagram

(b)