COREDES-SN datasheet(3/12 Pages) ACTEL

3 / 12 page

CoreDES

v4.0

CoreDES consists of four main blocks (shown in Figure 2).

1. Data schedule logic – computes the intermediate

data values at each round of the DES algorithm.

2. Iteration state machine logic – keeps track of

which round of the DES algorithm is currently in

progress.

3. Key schedule logic – computes the intermediate

keys at each round of the DES algorithm.

4. Parity

check

logic

–

checks

for

odd-parity

compliance of the 56 bits of cipher key and issues

an error signal if parity is not correct.

Design Security

Figure 3 shows a typical system diagram. Note

that the cipher key, which is the "secret" key, can be

made up of FPGA logic cells thereby preventing the

possibility of design or data theft. Actel Flash-based

devices (ProASICPLUS) employ FlashLockTM technology,

and Actel antifuse-based devices (Axcelerator, SX-A,

RT54SX-S) employ FuseLockTM technology, each of which

provides a means to keep the cipher key and the rest of

the logic secure. The output of the CoreDES macro

should be connected to registers or FIFOs, as it is only

valid

for

one

clock

cycle,

shown

the

sections"Encryption" on page 6 and "Decryption" on

page 7, respectively.

Figure 2 • CoreDes Block Diagram

Key

schedule

logic

Cipher Key

Parity Enable

Data In

Parity Error

Data Out

Iteration

state

machine

schedule

logic

Data

Parity

check

logic

Figure 3 • CoreDES in Typical System

Encrypted

Data

Output

To other logic or

global distribution,

e.g., Internet, etc.

Plaintext

(Unencrypted)

Data

Source

Local Device

Actel FPGA

CoreDES

Registers or

FIFO

Other

Logic

Other

Logic

Cipher

Key

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