CoreFIR

v3.0

7

CoreFIR Generator Parameters

The CoreFIR generates the RTL code for FIR filters with a variety of parameters. These parameters include generic FIR

parameters such as number of taps, number of input’s bits, number of coefficients’ bits, and data type, as well as

implementation parameters such as FPGA family, use embedded RAMs, system clock rate, and data sampling rate. The

CoreFIR supports the variations specified in Table 4.

Refer to "Appendix I: Sample Configuration File" on

page 12 for a sample usage of the parameters shown in

Table 4 in a configuration file for the CoreFIR Generator.

Detailed discussions about these parameters are in the

sections of this datasheet that follow.

Number of Taps (ntaps)

The FIR generator supports the number of taps specified

by the device families in Table 4. The variable ntaps in

the configuration file specifies the setting of this

parameter. Refer to "Appendix I: Sample Configuration

File" on page 12 for details.

Number of Bits of Inputs (nbits_in) and

Coefficients (nbits_coef)

The FIR Generator supports the number of bits of inputs

and coefficients for the device families specified in

Table 4. These parameters are set with the variables

nbits_in and nbits_coef in the configuration file. Refer to

"Appendix I: Sample Configuration File" on page 12 for

details.

Note: *coefi_en and ready are available when coef_fixed = 0.

Figure 3 • I/O Signals

Table 4 • CoreFIR Generator Configuration Parameters

Parameter Name

Description

Recommended Selection

AX

APA

SX-A

module_name

Name of generated module

–

–

–

nbits_input

Number of input’s bits of data

2 – 24

2 – 24

2 – 24

nbits_coef

Number of coefficients’ bits of data

2 – 24

2 – 24

2 – 24

ntaps

Number of taps

2 – 128

2 – 64

2 – 32

tap

Array of coefficients

–

–

–

data_signed

Data type: 0 = unsigned, 1 = signed

0,1

0,1

0,1

fpga_family

FPGA family

ax

apa

sxa

coef_fixed

0 = filter with configurable coefficients

1= filter with fixed coefficients

––

–

sys_clk_frq

Input clock frequency

–

–

–

sample_ratio

Sampling rate = sys_clk_frq/sample_ratio

Module_lang

Reserved. VHDL only.

VHDL

VHDL

VHDL

FIR

clk

rstn

datai_en

datai

datao_valid

coefi_en*

datao_valid

datao

ready*