CoreSDLC

v4.0

13

All bits of the rstat register are read only, except for bit 1, which is read/write.

Interframe Space Register (ifs)

The ifs register determines the minimum number of bit

times that must elapse between two consecutive

transmitted frames. CoreSDLC only takes the seven most

significant bits of the written value (only even numbers

can be used) and computes the interframe space by

counting this seven-bit number down to an all '0' value

twice. When read by the user’s software, the seven most

significant bits of the ifs register show the current count

value, while the least significant bit is a '1' for first

counting and a '0' for the second.

Interrupt Enable Register (ien1)

3

rdn

Receive done

When set, rdn indicates successful completion of a frame receive operation. The user can clear the rdn

bit by setting the gren bit.

2

rfne

Receive FIFO not empty

When set, rfne indicates that new data can be read from rfifo

1

gren

Receive enable

Setting this flag enables the receiver and clears the ovr, rcabt, ae, crce and rdn bits.

This bit is automatically cleared after the end of the receive operation.

0–

Not used

Note: This register has unimplemented bits (–). Unless otherwise noted, if these bits are read they will return '0'. Writing to these bits has

no effect.

Table 25 • ifs Register

MSB

LSB

ifs.7

ifs.6

ifs.5

ifs.4

ifs.3

ifs.2

ifs.1

ifs.0

Table 24 • rstat Register Bit Functions (Continued)

Bit

Symbol

Function

Table 26 • ien1 Register

MSB

LSB

––

––

egstv

–

egsre

egsrv

Table 27 • ien1 Register Bit Functions

Bit

Symbol

Function

7:4

–

Not used (fixed at 1100)

3

egstv

Transmit valid interrupt enable

2–

Not used

1

egsre

Receive error interrupt enable

0

egsrv

Receive valid interrupt enable

Note: This register has unimplemented bits (–). Unless otherwise noted, if these bits are read they will return ‘0’. Writing to these bits has

no effect.