LT3751EUFD datasheet(23/28 Pages) LINER

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LT3751

3751f

APPLICATIONS INFORMATION

Board Layout

The high voltage operation of the LT3751 demands careful at-

tention to the board layout, observing the following points:

1. Minimize the area of the high voltage end of the second-

ary winding.

2. Provide sufﬁcient spacing for all high voltage nodes

(NMOS drain, VOUT and secondary winding of the

transformer) in order to meet the breakdown voltage

requirements.

3. Keep the electrical path formed by CVTRANS, the primary

of T1, and the drain of the NMOS as short as possible.

Increasing the length of this path effectively increases

the leakage inductance of T1, potentially resulting in an

overvoltage condition on the drain of the NMOS.

4. Reduce the total node capacitance on the RVOUT and

RDCM pins by removing any ground or power planes

underneath the RDCM and RVOUT pads and traces.

Parasitic capacitance can cause unwanted behavior

on these pins.

5. Thermal vias should be added underneath the Exposed

Pad, Pin 21, to enhance the LT3751’s thermal perfor-

mance. These vias should go directly to a large area of

ground plane.

6. Isolated applications require galvanic separation of the

output-side ground and primary-side ground. Adequate

spacing between both ground planes is needed to meet

voltage safety requirements.

LT3751EUFD bảng dữ liệu(PDF) 23 Page - Linear Technology