LT3437IDD datasheet(24/28 Pages) LINER

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LT3437

3437fc

APPLICATIO S I FOR ATIO

Figure 10. Model for Loop Response

–

CURRENT MODE

POWER STAGE

gm = 1

gm = 650µ

1.25V

LT3437

ERROR

AMP

1.6M

ESR

OUTPUT

COUT

3437 F13

CFB

Figure 11. Overall Loop Response

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

–40

–20

–40

–20

100

10k

100k

3437 F12

VOUT = 3.3V

COUT = 100µF, 0.1Ω

CF = 330pF

RC = 25k

CC = 1500pF

ILOAD = 250mA

A zero can be added into the loop by placing a resistor (RC)

at the VC pin in series with the compensation capacitor, CC,

or by placing a capacitor (CFB) between the output and the

FB pin.

When using RC, the maximum value has two limitations.

First, the combination of output capacitor ESR and RC may

stop the loop rolling off altogether. Second, if the loop gain

is not rolled off sufficiently at the switching frequency,

output ripple will perturb the VC pin enough to cause

unstable duty cycle switching, similar to subharmonic

oscillations. If needed, an additional capacitor (CF) can be

added across the RC/CC network from the VC pin to ground

to further suppress VC ripple voltage.

With a tantalum output capacitor, the LT3437 already

includes a resistor (RC) and filter capacitor (CF) at the VC

pin (see Figures 10 and 11) to compensate the loop over

the entire VIN range (to allow for stable pulse skipping for

high VIN-to-VOUT ratios ≥ 10). A ceramic output capacitor

can still be used with a simple adjustment to the resistor RC

for stable operation (see Ceramic Capacitors section for

stabilizing LT3430). If additional phase margin is required,

a capacitor (CFB) can be inserted between the output and

FB pin, but care must be taken for high output voltage

applications. Sudden shorts to the output can create

unacceptably large negative transients on the FB pin.

For VIN-to-VOUT ratios < 10, higher loop bandwidths are

possible by readjusting the frequency compensation com-

ponents at the VC pin.

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and tem-

perature range. Proper loop compensation may be obtained

by empirical methods, as described in Application Notes

19 and 76.

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