CMS4A16LAF datasheet(9/46 Pages) FIDELIX

9 / 46 page

Rev. 0.5, May. ‘07

CMS4A16LAx–75Ex

7-6-5-4-3-2-1-0

7-0-1-2-3-4-5-6

1 1 1

4-5-6-7-0-1-2-3

1 0 0

5-4-7-6-1-0-3-2

5-6-7-0-1-2-3-4

1 0 1

6-7-4-5-2-3-0-1

6-7-0-1-2-3-4-5

1 1 0

1-0-3-2-5-4-7-6

1-2-3-4-5-6-7-0

0 0 1

2-3-0-1-6-7-4-5

2-3-4-5-6-7-0-1

0 1 0

3-2-1-0-7-6-5-4

3-4-5-6-7-0-1-2

0 1 1

3-2-1-0

3-0-1-2

1 1

A2 A1 A0

0-1-2-3-4-5-6-7

0 0 0

0-1-2-3

0 0

1-0-3-2

1-2-3-0

0 1

2-3-0-1

1 0

0-1

1-0

A1 A0

Not supported

Bn, Bn+1, Bn+2…..Bn,…

n=A0-A8(location 0-y)

Full Page(y)

Type=Interleaved

Type=Sequential

Order of Accesses within a Burst

Starting Column Address

Burst Length

Table 2. Burst Length Definition.

Operating Mode

The normal operating mode is selected by setting M7 and M8

to zero; the other combinations of values for M7 and M8 are

reserved for future use and/or test modes.Test modes

and reserved states should not be used because unknown

operation or incompatibility with future versions may result.

CAS Latency

The CAS latency is the delay, in clock cycles, between the

registration of a READ command and the availability of the

first piece of output data. The latency can be set to one, two,

or three clocks. If a READ command is registered at clock edge

r, and the latency is q clocks, the data will be available by clock

edge r + q. The DQs will start driving as a result of the clock

edge one cycle earlier (r + q- 1), and provided that the relevant

access times are met, the data will be valid by clock edge

r + q.

For example, assumi ng th at th e clock cycle time is

such that all relevant access times are met, if a READ

command is registered at T0 and the latency is programmed

to two clocks, the DQs will start driving after T1 and the data

w ill

v a l i d b y T 2 , a s s h o w n i n F i g u r e 2 .

Table 3 indicates the operating frequencies at which each CAS

latency setting can be used. Reserved states should not be

used as unknown operation or incompatibility with future

versions may result.

Write Burst Mode

When M9=0, the burst length programmed via M0-M2 applies to

both READ and WRITE bursts; when M9=1, the programmed

burst length applies to READ bursts, but write accesses are

single-location (non-burst) accesses.

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