ATR0635P1 datasheet(2/35 Pages) ATMEL

2 / 35 page

4979D–GPS–06/08

ATR0635P1

Description

The ATR0635P1 is a low-power, single-chip GPS receiver, especially designed to meet the

requirements of mobile applications. It is based on Atmel

®’s ANTARIS®4 technology and inte-

grates an RF front-end, filtering, and a baseband processor in a single, tiny 7 mm

× 10 mm

96 pin BGA package. Providing excellent RF performance with low noise figure and low power

consumption.

Due to the fully integrated design, just an RF SAW filter, a GPS TCXO and blocking capacitors

are required to realize a stand-alone GPS functionality.

The ATR0635P1 includes a complete GPS firmware, licensed from u-blox AG, which performs

the GPS operation, including tracking, acquisition, navigation and position data output. For nor-

mal PVT (Position/Velocity/Time) applications, there is no need for external Flash- or

ROM-memory.

The firmware supports e.g. the NMEA protocol (2.1 and 2.3), a binary protocol for PVT data,

configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS)

and A-GPS (aiding). It is also possible to store the configuration settings in an optional external

EEPROM.

Due to the integrated ARM7TDMI processor and an intelligent radio architecture, the

ATR0635P1 operates in a complete autonomous mode, utilizing on chip AGC in closed loop

operation.

For maximum performance, we recommend to use the ATR0635P1 together with a low noise

amplifier (e.g. ATR0610).

The ATR0635P1 supports assisted GPS.

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