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ATA5429-PLSW bảng dữ liệu(PDF) 31 Page - ATMEL Corporation

tên linh kiện ATA5429-PLSW
Giải thích chi tiết về linh kiện  UHF ASK/FSK Transceiver
PDF  100 Pages
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nhà sản xuất  ATMEL [ATMEL Corporation]
Trang chủ  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA5429-PLSW bảng dữ liệu(HTML) 31 Page - ATMEL Corporation

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31
4841D–WIRE–10/07
ATA5423/ATA5425/ATA5428/ATA5429
AVCC is the internal operation voltage of the RF transceiver and is fed by VS1 via the switch
SW_AVCC. AVCC must be blocked with a 68 nF capacitor (see Figure 2-1 on page 7, Figure 2.2
on page 8 and Figure 2-3 on page 9).
DVCC is the internal operation voltage of the digital control logic and is fed by VS1 or VSOUT
via the switch SW_DVCC. DVCC must be blocked on pin DVCC with 68 nF (see Figure 2-1 on
page 7, Figure 2.2 on page 8 and Figure 2-3 on page 9).
Pin VSOUT is a power supply output voltage for external devices (for example, microcontrollers)
and is fed by VS1 via the switch SW_VSOUT, or by the auxiliary voltage supply VAUX via
V_REG2. The voltage regulator V_REG2 regulates VSOUT to typically 3.25V. If the voltage reg-
ulator is active, a blocking capacitor of 2.2 µF has to be connected to VSOUT. VSOUT can be
switched off by the VSOUT_EN bit in control register 3 and is then reactivated by conditions
found in Figure 5-2 on page 32.
Pin N_RESET is set to low if the voltage V
VSOUT at pin VSOUT drops below 2.3V (typically) and
can be used as a reset signal for a connected microcontroller (see Figure 5-3 on page 34 and
Figure 5-4 on page 35).
Pin PWR_ON is an input to switch on the transceiver (active high).
Pin T1 to T5 are inputs for push buttons and can also be used to switch on the transceiver
(active low).
For current consumption reasons it is recommended to set T1 to T5 to GND, or PWR_ON to
VCC only temporarily. Otherwise, an additional current flows because of a 50 k
Ωpull-up resistor.
There are two voltage monitors generating the following signals (see Figure 5-1 on page 30):
• DVCC_OK if DVCC > 1.5V typically
• VSOUT_OK if VSOUT > V
Thres1 (2.3V typically)
• Low_Batt if VSOUT < V
Thres2 (2.38V typically)



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