UPSD3233 datasheet(162/170 Pages) STMICROELECTRONICS

162 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

162/170

Table 145. ISC Timing (3V Devices)

Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode.

2. For Program or Erase PLD only.

Figure 87. MCU Module AC Measurement I/O Waveform

Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.'

Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0'

Figure 88. PSD Module AC Float I/O Waveform

Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to

float when a 100mV change from the loaded VOH or VOL level occurs

IOL and IOH ≥ 20mA

Symbol

Parameter

Conditions

Min

Max

Unit

tISCCF

Clock (TCK, PC1) Frequency (except for PLD)

(Note 1)

MHz

tISCCH

Clock (TCK, PC1) High Time (except for PLD)

(Note 1)

tISCCL

Clock (TCK, PC1) Low Time (except for PLD)

(Note 1)

tISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note 2)

2MHz

tISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note 2)

240

tISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note 2)

240

tISCPSU

ISC Port Set Up Time

tISCPH

ISC Port Hold Up Time

tISCPCO

ISC Port Clock to Output

tISCPZV

ISC Port High-Impedance to Valid Output

tISCPVZ

ISC Port Valid Output to High-Impedance

AI06650

VCC – 0.5V

0.45V

Test Points

0.2 VCC – 0.1V

0.2 VCC + 0.9V

AI06651

Test Reference Points

VOL + 0.1V

VOH – 0.1V

VLOAD – 0.1V

VLOAD + 0.1V

0.2 VCC – 0.1V

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