UPSD3233 datasheet(71/170 Pages) STMICROELECTRONICS

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

I2C INTERFACE

There are two serial I2C ports implemented in the

uPSD323X Devices.

The serial port supports the twin line I2C-bus, con-

sists of a data line (SDAx) and a clock line (SCLx).

Depending on the configuration, the SDA and SCL

lines may require pull-up resistors.

■

SDA1, SCL1: the serial port line for DDC

Protocol

■

SDA2, SCL2: the serial port line for general

I2C bus connection

In both I2C interfaces, these lines also function as

I/O port lines as follows.

■

SDA1 / P4.0, SCL1 / P4.1, SDA2 / P3.6, SCL2

/ P3.7

The system is unique because data transport,

clock generation, address recognition and bus

control arbitration are all controlled by hardware.

The I2C serial I/O has complete autonomy in byte

handling and operates in 4 modes.

■

Master transmitter

■

Master receiver

■

Slave transmitter

■

Slave receiver

These functions are controlled by the SFRs.

■

SxCON: the control of byte handling and the

operation of 4 mode.

■

SxSTA: the contents of its register may also

be used as a vector to various service

routines.

■

SxDAT: data shift register.

■

SxADR: slave address register. Slave address

recognition is performed by On-Chip H/W.

Figure 39. Block Diagram of the I2C Bus Serial I/O

Table 50. Serial Control Register (SxCON: S1CON, S2CON)

543210

CR2

ENII

STA

STO

ADDR

CR1

CR0

AI06649

SCLx

SDAx

Bus Clock Generator

Arbitration and Sync. Logic

Shift Register

Status Register

Slave Address

Control Register

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