UPSD3233 datasheet(139/170 Pages) STMICROELECTRONICS

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

LU. 3 complementary static tests are required on

10 parts to assess the latch-up performance. A

supply overvoltage (applied to each power supply

pin) and a current injection (applied to each input,

output, and configurable I/O pin) are performed on

each sample. This test conforms to the EIA/JESD

78 IC Latch-up Standard (see Table 111). For

more details, refer to the Application Note,

AN1181.

DLU. Electro-static discharges (one positive then

one negative test) are applied to each pin of 3

samples when the micro is running to assess the

latch-up performance in dynamic mode. Power

supplies are set to the typical values, the oscillator

is connected as near as possible to the pins of the

micro, and the component is put in reset mode.

This test conforms to the IEC 1000-4-2 and

SAEJ1752/3 Standards (see Table 111). For more

details, refer to the Application Note, AN1181.

Table 111. Latch-up and Dynamic Latch-up Electrical Sensitivities

Note: 1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the JEDEC specifications.

This means when a device belongs to “Class A,” it exceeds the JEDEC standard. “Class B” strictly covers all of the JEDEC criteria

(International standards).

Symbol

Parameter

Conditions

Level/

Class(1)

Static Latch-up Class

TA = 25°C

DLU

Dynamic Latch-up Class

VDD = 5V; TA = 25°C; fOSC = 40MHz

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