ACS8525AP datasheet(7/112 Pages) SEMTECH

7 / 112 page

ACS8525A LC/P

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Revision 1.00/September 2007 © Semtech Corp.

Page 7

www.semtech.com

The ACS8525A is a highly integrated, single-chip solution

for “Hit-less” protection switching of SEC + Sync clock

“Groups”, from Master and Slave SETS clock cards and a

third (Stand-by) source, for Line Cards in a SONET or SDH

Network Element. The ACS8525A has fast activity

monitors on the SEC clock inputs and will implement

automatic system protection switching against failure of

the selected clock. The selection of the Master/Slave

input can be forced by a Force Fast Switch pin. The

Stand-by “Group” is selected if both the Master and Slave

input clocks fail, or, if not available, the device enters a

Digital Holdover mode.

Digital Phase Locked Loop (DPLL) and Direct Digital

Synthesis (DDS) methods are used in the device so that

the overall PLL characteristics are very stable and

consistent compared to traditional analog PLLs.

The ACS8525A has three SEC/SYNC input groups from

which it can select any group as input. It generates

independent clocks on outputs 01 and 02, with a total of

53 possible output frequencies, and generates two Sync

outputs on outputs FrSync and MFrSync: 8 kHz Frame

Synchronization (FrSync) signal and 2 kHz Multi-Frame

Synchronization (MFrSync) signal.

The device has three main operating modes (states);

Free-run, Locked, or Digital Holdover. In Free-Run mode,

the ACS8525A generates a stable, low-noise clock signal

at a frequency to the same accuracy as the external

oscillator, or it can be made more accurate via software

calibration to within ±0.02 ppm. In Locked mode, the

ACS8525A selects the most appropriate of the three input

SECs and generates a stable, low-noise clock signal

locked to the selected reference. In Digital Holdover

mode, the ACS8525A generates a stable, low-noise clock

signal, adjusted to match the frequency of the last

selected SEC.

One key architectural advantage that the ACS8525A has

over traditional solutions is in the use of DPLL technology

for precise and repeatable performance over temperature

or voltage variations and between parts. The overall PLL

bandwidth, loop damping, pull-in range and frequency

accuracy are all determined by digital parameters that

provide a consistent level of performance. An Analog PLL

(APLL) takes the signal from the DPLL output and provides

a lower jitter output. The APLL bandwidth is set four orders

of magnitude higher than the DPLL bandwidth. This

ensures that the overall system performance still

maintains the advantage of consistent behavior provided

by the digital approach.

The DPLLs are clocked by the external Oscillator module

(TCXO or XO) so that the Free-run or Digital Holdover

frequency stability is only determined by the stability of

the external oscillator module. This second key advantage

confines all temperature critical components to one well

defined and pre-calibrated module, whose performance

can be chosen to match the application.

All performance parameters of the DPLLs are

programmable without the need to understand detailed

PLL equations. Bandwidth, damping factor and lock range

can all be set directly.

The ACS8525A includes an SPI compatible serial

interface port, providing access to the configuration and

status registers for device setup, external control and

monitoring. The device is primarily controlled according to

values in this Register block.

Each register (8-bit wide data field) is identified and

referred to by its two-digit hexadecimal address and

name, e.g. Reg. 7D cnfg_interrupt. The “Register Map” on

page 38 summarizes the content of all of the registers,

and each register is individually described in the

subsequent Register Tables, organized in order of

ascending Address (hexadecimal), in the “Register

Descriptions” from page 42 onwards.

An Evaluation Board and intuitive GUI-based software

package is available for this device to help designers

learn how to use the ACS8525A and rapidly configure the

device for particular applications. This has its own

documentation: “ACS8525-EVB”.

The following description refers to the Block Diagram

(Figure 1 on page 1).

Inputs

The ACS8525A SETS device has input ports for input clock

groups from three sources, typically Master, Slave and

Stand-by, where each clock group comprises one SEC and

optionally one Sync signal. This is so that when any SEC

input changeover is made, the corresponding Sync signal

changeover is also made.

TTL/CMOS and PECL/LVDS ports are provided for the

Master and Slave SEC inputs to the device. The Stand-by

SEC input and three Frame Sync/Multi-frame Sync inputs

to the device are via TTL Ports. All the TTL/CMOS parts are

3 V compatible (with clamping if required by connecting

the VDDCLMP pin). Refer to the “Electrical Specifications”

General Description

ACS8525AP bảng dữ liệu(PDF) 7 Page - Semtech Corporation

ACS8525AP bảng dữ liệu(HTML) 7 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL