ATAR092 datasheet(18/107 Pages) ATMEL

18 / 107 page

4535E–4BMCU–05/07

ATAR092/ATAR892

Figure 4-17. Ceramic Resonator

Note:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta-

bilize oscillation before the oscillator output is used as system clock. This results in an additional

delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.

4.5.2.5

32-kHz Oscillator

Some applications require long-term time keeping or low resolution timing. In this case, an

on-chip, low power 32-kHz crystal oscillator can be used to generate both the SUBCL and the

SYSCL. In this mode, power consumption is greatly reduced. The 32-kHz crystal oscillator can

not be stopped while the power-down mode is in operation.

Figure 4-18. 32-kHz Crystal Oscillator

Note:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta-

bilize oscillation before the oscillator output is used as system clock. This results in an additional

delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.

4.5.3

Clock Management

The clock management register controls the system clock divider and synchronization stage.

Writing to this register triggers the synchronization cycle.

OSC1

Oscin

Oscout

4Out

Stop

4Out

Osc-Stop

OSC2

Cer.

Res

Mask Option

Oscillator

4 MHz

OSC1

Oscin

Oscout

32Out

OSC2

XTAL

32 MHz

Mask Option

Oscillator

32 kHz

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