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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AT89C5131A-RDTIL bảng dữ liệu(PDF) 69 Page - ATMEL Corporation |
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AT89C5131A-RDTIL bảng dữ liệu(HTML) 69 Page - ATMEL Corporation |
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69 / 186 page  69 AT89C5131A-L 4338F–USB–08/07 SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 37. Baud Rate Selection Baud Rate Selection Table for UART Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register. 7 6 5 4 3 2 1 0 RCLK / 16 RBCK INT_BRG 0 1 TIMER1 0 1 0 1 TIMER2 INT_BRG TIMER1 TIMER2 TIMER_BRG_RX Rx Clock / 16 0 1 TIMER_BRG_TX Tx Clock TBCK TCLK TCLK (T2CON) RCLK (T2CON) TBCK (BDRCON) RBCK (BDRCON) Clock Source UART Tx Clock Source UART Rx 0 0 0 0 Timer 1 Timer 1 1 0 0 0 Timer 2 Timer 1 0 1 0 0 Timer 1 Timer 2 1 1 0 0 Timer 2 Timer 2 X 0 1 0 INT_BRG Timer 1 X 1 1 0 INT_BRG Timer 2 0 X 0 1 Timer 1 INT_BRG 1 X 0 1 Timer 2 INT_BRG X X 1 1 INT_BRG INT_BRG |
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