2

4110K–AERO–11/07

MH1RT

Notes:

1. Nominal 2 Input NAND Gate FO = 2 at 3.3V.

Design

Design Systems

Supported

Atmel supports several major software systems for design with complete macro cell libraries, as

well as utilities for checking the netlist and estimated pre-route delay simulations.

The following design systems are supported:

Table 1. List of Available MH1RT Matrices

Device

Number

Typical Routable

Gates

Max Pad

Count

Max

I/O Count

Gate

Max. Sites Count

MH1099E

519,000

332

324

180 ps

920,385

MH1156E

764,000

412

404

180 ps

1,447,975

MH1242E

1,198,000

512

504

180 ps

2,275,377

MH1332E

1,634,000

596

588

180 ps

3,098,804

Table 2. Supported design systems

System

Available Tools

Cadence

Verilog-XL

BuildGates

Mentor/Model Tech

Modelsim Verilog and VHDL (VITAL) Simulator

DFT- Scan insertion and ATPG, BIST

Synopsys

®

Design Compiler™ - Synthesis

Primetime

Formality