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CS42888-CQZ bảng dữ liệu(PDF) 37 Page - Cirrus Logic |
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CS42888-CQZ bảng dữ liệu(HTML) 37 Page - Cirrus Logic |
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37 / 61 page ![]() DS717F2 37 CS42888 side of the board as the CS42888 to minimize inductance effects. All signals, especially clocks, should be kept away from the ADC/DAC_FILT+, VQ pins in order to avoid unwanted coupling into the modulators. The ADC/DAC_FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path from ADC/DAC_FILT+ and AGND. The CDB42448 evaluation board demonstrates the opti- mum layout and power supply arrangements. For optimal heat dissipation from the package, it is recommended that the area directly under the part be filled with copper and tied to the ground plane. The use of vias connecting the topside ground to the back- side ground is also recommended. |
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