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AT90SC6404RT

6511AS–SMIC–28Feb05

Description

The AT90SC6404RT is a low-power, high-performance, 8/16-bit microcontroller with ROM program memory, EEPROM

data memory, based on the secureAVR enhanced RISC architecture. By executing powerful instructions in a single clock

cycle, the AT90SC6404RT achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32 general-

purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single

instruction executed in one clock cycle.

The AT90SC6404RT uses the secureAVR that allows the linear addressing of up to 8M bytes of code and up to 16M bytes

of data as well as a number of new functional and security features.

The ability to map the EEPROM in the code space allows parts of the program memory to be reprogrammed in-system.

This technology combined with the versatile 8/16-bit CPU on a monolithic chip provides a highly flexible and cost-effective

solution to many smart card applications.

Additional security features include power, frequency and temperature protection logic, logical scrambling on program data

and addresses, Power Analysis countermeasures and memory accesses controlled by a supervisor mode.

Figure 1 shows the AT90SC6404RT block diagram.

Figure 1. AT90SC6404RT secureAVR Enhanced RISC Architecture

Instruction

Decoder

Program

Memory

Instruction

Register

Access

Control

General

Purpose

Registers

X

Y

Z

Status

Register

RAM

Data Memory

Interrupt

Unit

ISO 7816

I/O Port 0

Timer

Control

Lines

ALU

EEPROM

User Memory

OTP

PC

Secure

Control

GND

CLK

Access

Control

IN/OUT0

Data Bus

8-bit

RNG

16

16

16

8

88

DPA Counter

measures

Reset

Circuit

RST

ISO 7816

Controller

CRC and

Checksum

Accelerator

DES/

Triple DES