CS5531-AS datasheet(44/50 Pages) CIRRUS

44 / 50 page

CS5531/32/33/34-AS

DS289F5

3. PIN DESCRIPTIONS

Clock Generator

OSC1; OSC2 - Master Clock.

An inverting amplifier inside the chip is connected between these pins and can be used with a

crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible)

clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock

for the device.

Control Pins and Serial Data I/O

CS - Chip Select.

When active low, the port will recognize SCLK. When high the SDO pin will output a high

impedance state. CS should be changed when SCLK = 0.

817

CS5533/4

VREF+

VREF-

DGND

SDO

SERIAL DATA INPUT

POSITIVE ANALOG POWER

AMPLIFIER CAPACITOR CONNECT

DIFFERENTIAL ANALOG INPUT

CHIP SELECT

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

POSITIVE DIGITAL POWER

DIGITAL GROUND

SERIAL DATA OUT

MASTER CLOCK

DIFFERENTIAL ANALOG INPUT

AIN3+

AIN3-

SDI

VD+

NEGATIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

AIN2-

AIN2+

VA-

VA+

AIN4-

AIN4+

OSC1

OSC2

AIN1-

AIN1+

SCLK

SERIAL CLOCK INPUT

LOGIC OUTPUT (ANALOG)/GUARD

LOGIC OUTPUT (ANALOG)

MASTER CLOCK

813

VREF+

VREF-

SCLK

DGND

VA-

VA+

AIN1-

AIN1+

SDO

OSC1

OSC2

SERIAL DATA INPUT

LOGIC OUTPUT (ANALOG)/GUARD

POSITIVE ANALOG POWER

AMPLIFIER CAPACITOR CONNECT

DIFFERENTIAL ANALOG INPUT

CHIP SELECT

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

SERIAL CLOCK INPUT

POSITIVE DIGITAL POWER

DIGITAL GROUND

SERIAL DATA OUT

MASTER CLOCK

CS5531/2

DIFFERENTIAL ANALOG INPUT

AIN2+

AIN2-

SDI

VD+

NEGATIVE ANALOG POWER

MASTER CLOCK

LOGIC OUTPUT (ANALOG)

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